1. Field
Apparatus and methods described in this document relate to electronic circuit designs. More particularly, the apparatus and methods relate to Metal-Oxide-Semiconductor circuits, and to methods for powering down such circuits.
2. Background
Many active filters, analog-to-digital converters (ADCs), and other circuits fabricated with Complimentary Metal-Oxide-Semiconductor (CMOS) devices are designed and implemented using switched capacitor techniques. CMOS switched capacitor circuits may employ CMOS transistors and capacitors.
Higher levels of system integration are desired in many electronic systems, including cellular telephones, because integration offers lower production costs and allows more functions to be packed into smaller footprints and volumes. Modern cellular telephones feature functions such as games, video, and music, in addition to wireless telephony. These and other functions may be implemented using mixed analog/digital circuits in CMOS fabrication technologies.
The needs for high levels of integration, lower costs, and higher speeds are driving CMOS technology deeper into nanometer scale. At this time, CMOS devices may be fabricated using 65 nm and even smaller feature-size devices. The scale of CMOS devices is likely to continue to decrease in the future.
As transistor dimensions shrink down to nanometer scales, power supply voltage is generally also reduced in order to keep the electric field strength constant and ensure lifetime device reliability. In the case of 65 nm devices, their power supply voltage may be brought down to 1.1 volts and possibly lower. The reason for low supply voltages is that as CMOS technology advances to finer (or thinner) scales/geometries, transistor breakdown voltages are reduced. At the same time, certain design blocks typically use higher power supply voltages, which may be about 2.1 volts or 3.3 volts. Such blocks may include high-speed universal serial bus (USB) and audio coder-decoder (CODEC) blocks. The minimum supply voltage of a CODEC may be determined by the audio power that is delivered to the speakers, or by maximum input signal voltage that is processed by the CODEC. The minimum supply voltage of a USB interface block may be dictated by the applicable USB specification. Thus, selection of power supply voltages for USB, CODEC, and other blocks may be driven by external considerations.
It may be desirable for a single semiconductor chip to have two different types (scales, geometries, or sizes) of CMOS transistors, with one type adapted for operation at a low supply voltage and another type adapted for a higher supply voltage. The low supply voltage transistors, referred to herein as core transistors, have a relatively thin gate oxide layer to increase speed at low voltage. These transistors may be in the central part of the chip and may be optimized with the current state of process engineering for packing density and high performance. The high supply voltage transistors are usually used to interface with external devices/chips and are hence referred to as the input/output (I/O or IO) transistors. These transistors are larger than core transistors, and have a relatively thick gate oxide layer for reliable high voltage operation.
Because of the integration, cost, and speed constraints, there is a need in the art to provide CMOS circuits fabricated at relatively small scales, but that use relatively high power supply voltages. There is also a need in the art for operating such circuits with the relatively high power supply voltages without overstressing the individual devices of the circuits. Furthermore, there is a need in the art for combining two different types of CMOS devices on a single chip, with one type adapted for operation at a relatively low supply voltage, and another type adapted for operation at a relatively high supply voltage.